VTS 2010 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Social Activities -- Workshop Registration -- More Information -- Committees

Scope

The IEEE VLSI Test Symposium explores emerging trends and novel concepts in the testing of integrated circuits and systems. The symposium is a leading international forum where many of the world's leading test experts and professionals from both industry and academia join to present and debate key issues in testing. VTS 2010 addresses key trends and challenges in the semiconductor design and manufacturing industries through an exciting program that includes Keynote and Plenary Talks, Technical Paper Sessions, Panels, New Topic Sessions, Full-day Tutorials, co-located Workshops, and the Innovative Practices Track.

TECHNICAL PAPER SESSIONS will present the latest research results in test, including:

Analog/Mixed-Signal Test
ATPG and Compression
Delay and Performance Test
Low-power IC Test
Memory Test and Repair
NBTI and Early Life Failures
On-line and System Testing
RF Test
Test for Emerging Technologies
Test Optimizations
Transient and Soft Errors
Yield Modeling and Defects

EMBEDDED TUTORIAL

Test and Fault Tolerance of Networks-on-Chip

INNOVATIVE PRACTICES (IP) TRACK highlights:

Practices in RF Test
Industrial Practices for Test Cost Reduction
Verification and Testing Challenges in High-Level Synthesis
Implications of Power Delivery Network for Validation and Testing
Post-Silicon Debug
3D Chip Testing

FEATURED PANELS:

Adaptive Analog Test
Apprentice – VTS Edition: Season 3;
Low-Power Test and Noise-Aware Test
EDA for Analog DFT/ATPG

HOT TOPIC SESSIONS

Design Consideration and Silicon Evaluation of On-Chip Monitors
MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture and Its Impact
Mixed-Signal Test Impact to SoC Commercialization
3-D Testing
Test Facilities and Infrastructure in Canada
Hardware Security: Test and Verification Issues

OTHER SESSIONS

Thesis Research Posters
E.J. McCluskey Doctoral Thesis Competition

Social Activities

top

VTS provides an opportunity for informal technical discussions among participants. This year, the social program will feature a visit to a local attraction (transportation provided) and a banquet sunset dinner on the beach. Attendees will also receive complementary breakfast, lunch and breaks each day of the conference. Santa Cruz, California provides a very attractive backdrop for all VTS 2010 activities. We are sure that you will find VTS 2010 enlightening, thought-provoking, rewarding, and enjoyable!

Workshop Registration

top

For a Preliminary Program, Conference Registration and Hotel Information please visit:
http://www.tttc-vts.org

More Information

top

GENERALCHAIR
Magdy Abadir
Freescale Semiconductor
Email: M.Abadir@freescale.com

PROGRAM CO-CHAIR
Claude Thibeault
Écolede Tech. Supérieure
Email: claude.thibeault@etsmtl.ca

PROGRAM CO-CHAIR
Michel Renovell
LIRMM-CNRS
Email: renovell@lirmm.fr

Committees

top

General Chair
M. Abadir - Freescale

Program Chairs
M. Renovell - LIRMM/CNRS
C. Thibeault - ETS

Vice-General Chairs
P. Maxwell - Aptina
C. Metra - U. Bologna

Vice-Program Chair
R. Galivanche - Intel Corp.

New Topics
B. Courtois - TIMA
B. Kaminska - Simon Fraser U.

Special Sessions
L. Anghel - TIMA
C.P. Ravikumar - Texas Instr

Innovative Practices Track
K. Hatayama - STARC
S. Mitra - Stanford U

Registration
D. Gizopoulos - UNIPI
S. Ozev - Arizona

Publicity

Chair:	S. Ravi - Texas Instruments
Members:	Ismet Bayraktaroglu - Sun Microsystems Stefano Di Carlo - Politecnico di Torino Giorgio DI Natale - LIRMM

Publications
Y. Makris - Yale University

Awards
S. Hellebrand - U Paderborn

Finance
C.H. Chiang - Alcatel-Lucent

Local Arrangements
Li Wang - Univ. of Calif. at Santa Barbara

Members:

Vishal Mehta - NVidia
Sean Wu - Univ. of Calif. at Santa Barbara

Corporate Support
B. Cory - Nvidia

International Liaisons

Latin America:	V. Champac - INAOEP Mexico
Midlle East & Africa:	R. Makki - UAE U
Asia Pacific:	Y. Sato - Hitachi
Asia & Taiwan:	C-W. Wu - NTHU
Eastern Europe:	V. Hahanov - KHNURE Ukraine
Western Europe:	Z. Peng - Linkoping U

Ex-Officio
Y. Zorian - Virage Logic

Program Committee

J. Abraham - University of Texas at Austin
V. Agrawal - Auburn University
D. Appello - STMicroelectronics
K. Arabi - Qualcomm
B. Becker - University of Freiburg
J. Bhadra - Freescale Semiconductor Inc.
K. Chakrabarty - Duke University
A. Chatterjee - Georgia Tech
C.J. Clark - Intellitech Corporation
P. Girard - LIRMM
X. Gu - Cisco
S. Gupta - University of Southern California
I. Hartanto - Xilinx
A. Khoche - Verigy, Inc
H. Konuk - Broadcom
X. Li - Chinese Academy of Sciences
F. Lombardi - Northeastern University
M. Lubaszewski - UFRGS
E.J. Marinissen - IMEC
S. Mourad - Santa Clara University
Z. Navabi - Northeastern University
A. Raghunathan - Purdue University
J. Rajski - Mentor Graphics Corporation
S. Reddy - U. Iowa
K. Roy - Purdue Univ.
J. Segura - University of Illes Balears
S. Shoukourian - Virage Logic
M. Soma - Univ. of Washington
S. Sunter - LogicVision
M. Tehranipoor - U. Connecticut
J. Tyszer - Poznan University of Technology
R. Ubar - Tallin U
C.J. Wu - National Tsing Hua University
H. Wunderlich - Universitat Stuttgart

Steering Committee

J. Figueras - U Pol Catalunya
A. Ivanov - UBC
M. Nicolaidis - TIMA
P. Prinetto - Polit di Torino
A. Singh - Auburn U
P. Varma - Blue Pearl
Y. Zorian - Virage Logic

For more information, visit us on the web at: http://www.tttc-vts.org

The 28th IEEE VLSI Test Symposium (VTS2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).

TTTC's Electronic Broadcasting Service
	28th IEEE VLSI TEST SYMPOSIUM (VTS 2010) April 19th – April 22nd, 2010 Seascape Beach Resort, Santa Cruz California, USA http://www.tttc-vts.org